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Senior RTL Engineer, Interconnect Design

OpenAI

San Francisco·$225,000 - $445,000

$225,000 - $445,000

entry

RemoteSoftware engineeringVerified

Source checked 1 hour ago.

Posted 1 month ago.

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ABOUT THE TEAM

OpenAI's Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads.
Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models.
By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI's supercomputing platform.

ABOUT THE ROLE

We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform.
You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale.
This is a senior, hands-on engineering role with broad technical ownership. You will drive design from

requirements

through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness.

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